Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies

Abstract This study analyzes the memory hierarchy performance of three SPEC benchmarks and two TPC benchmarks. It nds large di erences between the benchmarks in instruction cache miss rates and smaller di erences in data cache miss rates. It then breaks all of the miss rates down in their components: context switch misses, user misses, supervisor misses, and collision misses. It demonstrates that context switches contribute little to the miss rates as do collision misses. Finally, using temporal locality graphs, it shows that the inherent locality di erences between the reference streams is the main cause of miss rate di erences between the various benchmarks.